Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use In ferroelectric semiconductor memory devices. Other ferroelectric materials, for example, strontium bismuth tantalate (SBT) can also be used. The ferroelectric material Is located between two electrodes to form a ferroelectric capacitor for storing information. Ferroelectric capacitor uses the hysteresis polarization characteristic of the ferroelectric material for storing information. The logic value stored in the memory cell depends on the polarization of the ferroelectric capacitor. To change the polarization of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. The polarization of the capacitor depends on the polarity of the voltage applied. An advantage of the ferroelectric capacitor is that It retains its polarization state after power is removed, resulting in a non-volatile memory cell.
FIG. 1 shows a plurality of ferroelectric memory cells configured in a group 103. Such a memory architecture is described in, for example, Takashima et al., IEEE J. Solid-State Circuits, vol. 33, pp 787-792, May 1998, which Is herein Incorporated by reference for all purposes. The group, for example, comprises 8 memory cells. Groups of other sizes are also useful. Preferably, the number of cells within a group is equal to 2y, where y=a whole number≧1. The memory cells 140 of the group, each with a transistor 142 coupled to a ferroelectric capacitor 144 in parallel, are coupled in series. The gates of the cell transistors are, for example, gate conductors which either serve as or are coupled to wordlines 160. One end of the group is coupled to a bitline 150 via a block select transistor 108 while the other end is coupled to a plateline 170. A plurality of groups are Interconnected by wordlines to form a memory block or array.
FIG. 2 shows a cross-section of a conventional memory group 103. As shown, the transistors 142 of the memory cells are formed on a substrate 205. Adjacent cell transistors share a common diffusion region. The capacitors 144 of the memory group are arranged in pairs. The bottom electrode 246 serves as a common electrode for adjacent capacitors. The bottom capacitor electrodes are each coupled to the cell transistors via plugs 274. The top electrode 248 of a capacitor from a capacitor pair is coupled to the top electrode of a capacitor of an adjacent pair. The top capacitor electrodes are coupled to the cell transistors via top electrode plugs 276.
FIGS. 3-4 show a portion of the process for forming a conventional ferroelectric memory group 103. Referring to FIG. 3, a substrate 105 with a partially formed memory cell 140 of a memory group is provided. As shown, the front end of line (FEOL) portion of the memory cell is formed (e.g., up to the formation of the contact that couples the top capacitor electrode to the cell transistor). The partially formed memory cell includes a transistor 142 with first and second diffusion regions 338 and 339. A ferroelectric capacitor 144 is provided. The ferroelectric capacitor includes a ferroelectric layer 349 between top and bottom electrodes 248 and 246. The bottom electrode Is a common electrode with a capacitor of an adjacent memory cell. The bottom electrode Is coupled to the first diffusion region of the transistor via a bottom electrode plug 274. To prevent oxidation of the plug, a barrier layer 368 is disposed between the bottom electrode and plug. An encapsulation layer 384 is also provided to cover the capacitors. The encapsulation layer protects the capacitors from hydrogen. Additionally, the encapsulation protects the plug 274 from oxygen.
Conventionally, the plug that connects the top electrode (active area top electrode plug or AATE plug) to the second diffusion region of the transistor is formed in two separate process steps. As shown, the partially formed memory cell Includes a lower portion 376 of the AATE plug. A barrier layer 382 is provided above the lower portion of the AATE plug. The barrier layer serves to prevent oxygen from oxidizing the plug 376. Referring to FIG. 4, the process continues by forming upper portion of the AATE plug. A resist layer is deposited over the ILD and patterned to form an etch mask, exposing portions of the ILD. An anisotropic etch is performed to remove the exposed portions of the ILD, forming vias 472. Due to the depth of via 472, the sidewalls have a non-vertical profile (e.g., slanted).
Subsequently, a barrier layer 492 is deposited over the substrate to line the sidewalls and bottom of the vias. The barrier layer, for example, comprises silicon nitride or aluminum oxide. A reactive ion etch (RIE) is performed to remove the horizontal components of the barrier layer, leaving it lining only the sidewalls of the vias while exposing the lower portion of the plug and top capacitor electrodes. However, due to the slanted profile of via 472, the etch also removes some of the barrier material lining the sidewalls, compromising the integrity of the barrier. This can lead to failures since hydrogen can now penetrate to the capacitor, degrading the properties of the ferroelectric material.
From the foregoing discussion, it is desirable to provide an AATE plug with improved sidewall profile to increase reliability.